AMD NPU Kernel Documentation Overview

Architecture and Driver Management

The documentation identifies the AMD NPU as a multi-user AI inference accelerator integrated into AMD client APUs. It enables efficient execution of Machine Learning applications like CNN and LLM. The hardware is based on the AMD XDNA Architecture and is managed by the amdxdna driver. This description establishes the fundamental role of the NPU within the Linux kernel ecosystem for local AI inference tasks.

Hardware Topology and Partitioning

The XDNA Array comprises a 2D array of compute and memory tiles built with AMD AI Engine Technology. Each column contains four rows of compute tiles and one memory tile acting as L2 memory. The array can be partitioned at column boundaries to create spatially isolated partitions bound to workload contexts. Specific client NPUs, such as AMD Phoenix and Hawk Point, utilize a 4x5 topology.